In current digital circuit designs, for example, in ASIC and programmable gate array designs, power and timing optimization is done on a per path basis. Standard techniques involve 1) changing the circuit power level, i.e., implementing higher (faster) or lower power versions of the same book (logic gate(s)) to meet the timing requirement of a critical path; 2) repower, either serially with a repowering tree, or in parallel by cloning or duplicating a path to speed up the critical nets. As a consequence of these methods, unnecessary loading of noncritical nets occur resulting in wasted AC power. In addition, increased wire congestion can occur as the number of books that the input nets have to fan out to doubles/triples to meet the performance paths.
With more particularity, FIG. 1a shows a logic network 10 having a timing critical path starting at primary input pin C of NAND gate 1 going to input pin A of NAND gate 2, and on to the critical output 15 of NAND gate 2. Assume that all other paths 16-20 are non-timing critical. Thus, FIG. 1a illustrates the very common occurrence of critical timing paths crossing non-critical timing paths on a logic network. There are three ways to correct the timing problems in this network: 1) increase NAND 1 to the highest power level required to correct the problem. If this can correct the timing problem, it will, at the very least, increase the power of the non-critical path through input pin A of NAND 1; 2) if increasing the power level of the circuit does not solve the timing problem then: a) either serial repowering comprising the addition of a serial buffer 21 to the book of FIG. 1a, as shown in FIG. 1b; or, b) parallel repowering comprising the addition of logic NAND gate 23 duplicate of logic NAND gate 1 and connected in parallel with the original NAND gate 1, as shown in FIG. 1c. In both cases, power consumption, as well as wiring congestion, is increased by adding books. Thus, those non-critical paths 16-20 that cross critical paths are not power-optimized. This is because in order to obtain an optimal performance/power solution, the non-critical capacitance must be eliminated from the critical path to speed it up without increasing overall capacitance. FIG. 1(b) only provides partial isolation of the critical capacitance C.sub.crit from the non-critical capacitance C.sub.non-crit since gate 1 still sees the load of the buffer. FIG. 1(c) doubles the input capacitance of both the critical and non-critical paths, as well as increasing the area and wiring congestion.
Prior art techniques for optimizing (critical path) performance in such circuit designs may be found and described in U.S. Pat. No. 4,827,428 which describes a transistor sizing system for improving the design of integrated circuits; U.S. Pat. No. 4,940,908 which describes a technique for reducing critical speed path delays in binary logic circuits by implementing "multiplexing logic", U.S. Pat. No. 5,815,004 which teaches a FPGA having independently buffered output lines of a configurable logic block for handling critical path situations; U.S. Pat. No. 5,517,132 which teaches a logic synthesis method utilizing two voltages, a higher voltage for driving critical paths and lower level voltages for driving non-critical paths, in an effort to reduce power consumption of integrated circuits; and, U.S. Pat. No. 5,787,011 which teaches a technique implementing complementary passage logic (CPL) technology using low power circuits for non-critical circuits and higher power circuits for critical paths. While effective for their respective purposes, it still remains the case that non-critical paths that cross critical paths cannot be power-optimized.
As shown in FIG. 2, the basic problem with traditional libraries is that a traditional book 25 comprising a logic stage 27 for receiving input signals and implementing logic, and a single output buffer stage 29 having a single output for driving fanout circuits is designed for a given power level. Moreover, these book designs assume that both inputs are equally critical and all output sinks are also critical paths. As shown in FIG. 1(a), however, this is simply not the case.
What is required is a book design technique that can simultaneously support a critical high-performance/high-power path, and a non-critical low-power path, thus allowing simultaneous optimization of both power and performance.